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176 Catalyst Supervisor Engine Security
Podcast Episode 176
Release Date: July 17, 2008
Jamey Heary who wrote up an article for Network World’s Subnet on April 22 and I really liked his description so I will continue to borrow it: The Cisco Catalyst 6500 supervisor engine 32-PISA is the fastest and most feature rich access layer sup engine Cisco has ever produced. The PISA is the result of years of R&D research and testing. For the first time ever, Cisco has added a special Network processing unit (NPU) daughter card to the sup32 engine. It is called the programmable IP Services Accelerator or PISA for short. The PISA NPU consists of 16 micro engines and a hardware crypto card. The big advantage of the PISA architecture is that, unlike asic technology, you can re-program the PISA micro engines whenever the need arises. This means the shelf life and flexibility of the PISA will be longer than an equivalent asic based solution. Not even Cisco’s sup720 has this kind of technology. The beauty of the thing is that the underlying architecture, code base, and PFC are the exact same as the venerable supervisor 32 engine. This means that the same features the original sup32 supported will be supported in the new sup32-PISA. *minor caveats/differences do exist though so be sure to read the release notes.
Release Date: July 17, 2008
Jamey Heary who wrote up an article for Network World’s Subnet on April 22 and I really liked his description so I will continue to borrow it: The Cisco Catalyst 6500 supervisor engine 32-PISA is the fastest and most feature rich access layer sup engine Cisco has ever produced. The PISA is the result of years of R&D research and testing. For the first time ever, Cisco has added a special Network processing unit (NPU) daughter card to the sup32 engine. It is called the programmable IP Services Accelerator or PISA for short. The PISA NPU consists of 16 micro engines and a hardware crypto card. The big advantage of the PISA architecture is that, unlike asic technology, you can re-program the PISA micro engines whenever the need arises. This means the shelf life and flexibility of the PISA will be longer than an equivalent asic based solution. Not even Cisco’s sup720 has this kind of technology. The beauty of the thing is that the underlying architecture, code base, and PFC are the exact same as the venerable supervisor 32 engine. This means that the same features the original sup32 supported will be supported in the new sup32-PISA. *minor caveats/differences do exist though so be sure to read the release notes.
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